1. Field of Invention
Our invention relates generally to the transmission of digital data signals from one integrated circuit chip to another and more particularly to a method and electronic network for limiting electrical noise arising during the transmission.
2. Description of Prior Art
As is well known in the data processing art, information may be represented within the processing equipment as digital data words composed of a series of data bits. The bits are in actuality high and low electrical signal levels which are produced by controlling the conduction state of semiconductor elements such as bipolar transistors, field effect transistors, diodes, etc. These semiconductor elements are typically found in integrated circuit chips, the chips being interconnected to carry out the desired processing. In this arrangement, it is common to have the circuits of a first chip perform one or more operation, as for example logic functions, on a data word and to thereafter forward the data word i.e., bits to a second chip for further processing.
Workers have found that difficulties can arise in the course of transmitting data words from a first very large scale integrated (VLSI) circuit chip termed for convenience the "transmit chip" to a second VLSI chip, termed for convenience the "receive chip". Particularly, the ability of the chip interconnections to forward bits i.e., signals, without distortion may be exceeded. It has been found that if the multiple output devices which produce the transmit chip output signals are simultaneously switched to the conduction state i.e., switched to low resistance, the resulting currents contributed by the distributed capacitance of the interconnections may adversely affect the accuracy of the transmitted word. The capacitive currents contributed by the interconnection act as electrical noise which modifies the transmitted signal levels.
Workers have found that one approach to this problem is to prevent all of the output devices of the transmit chip from simultaneously switching to the conduction state. In this way, the capacitive currents contributed by the interconnections are maintained at an acceptable level. However, this approach has drawbacks. Particularly, by constraining the output devices, more time is required to fully transmit signals between chips.
An alternative to constraining the conduction state of the transmit chip output devices is to provide interconnections between chips of dimensions which minimized the distributive capacitance e.g., increased spacing between conductive elements. Unfortunately, however, due to size limitations necessary to achieve the high component packing density of VLSI circuits it has been found impractical to make the interconnections of larger spacing. In fact, continuing pressure by designers to increase component packing density has encouraged further limitation of interconnection size, thus aggravating the problem.